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Omni
General Description
ision
TM
Advanced Information Preliminary Datasheet
OV9650 Color CMOS SXGA (1.3 MegaPixel) CAMERACHIPTM with OmniPixelTM Technology Applications
* * * * Cellular and Picture Phones Toys PC Multimedia Digital Still Cameras
The OV9650 CAMERACHIPTM is a low voltage CMOS image sensors that provides the full functionality of a single-chip SXGA (1280x1024) camera and image processor in a small footprint package. The OV9650 provides full-frame, sub-sampled or windowed 8-bit/10-bit images in a wide range of formats, controlled through the Serial Camera Control Bus (SCCB) interface. This product has an image array capable of operating at up to 15 frames per second (fps) in SXGA resolution with complete user control over image quality, formatting and output data transfer. All required image processing functions, including exposure control, gamma, white balance, color saturation, hue control, white pixel canceling, noise canceling, and more, are also programmable through the SCCB interface. In addition, OmniVision CAMERACHIPS use proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable color image.
Key Specifications
Power Supply Power Requirements Temperature Range Active Array Size Core Analog I/O Active Standby Operation Stable Image 1300 x 1028 1.8VDC + 10% 2.45 to 2.8 VDC 2.5V to (VDD-A+0.3V) 50 mW (15 fps, no I/O power) 30 W -20C to 70C 0C to 50C * YUV/YCbCr 4:2:2 * GRB 4:2:2 * Raw RGB Data 1/4" 15 fps 30 fps 60 fps 120 fps 0.9 v/Lux-sec 40 dB 62 dB Progressive 1050 x tROW Programmable 3.18 m x 3.18 m 30 mV/s at 60C 28 K e <0.03% of VPEAK-TO-PEAK 4.13 mm x 3.28 mm 5095 m x 5715 m
Output Formats (8-bit) Lens Size SXGA Maximum VGA Image QVGA, QQVGA, CIF Transfer Rate QCIF, QQCIF Sensitivity S/N Ratio Dynamic Range Scan Mode Maximum Exposure Interval Gamma Correction Pixel Size Dark Current Well Capacity Fixed Pattern Noise Image Area Package Dimensions
Features
* * * * High sensitivity for low-light operation Low operating voltage for embedded portable applications Standard SCCB interface Supports SXGA, VGA, QVGA, QQVGA, CIF, QCIF, QQCIF, and windowed outputs with Raw RGB, RGB (GRB 4:2:2), YUV (4:2:2) and YCbCr (4:2:2) formats VarioPixelTM method for sub-sampling formats (VGA, QVGA, QQVGA, CIF, QCIF, and QQCIF) Automatic image control functions including: Automatic Exposure Control (AEC), Automatic Gain Control (AGC), Automatic White Balance (AWB), and Automatic Black-Level Calibration (ABLC) Image quality controls including color saturation, hue, gamma, sharpness (edge enhancement), lens correction, white pixel canceling, and noise canceling
* *
Figure 1 OV9650 Pin Diagram
A1 PWDN B1 VREF C1 A2 AVDD B2 NVDD C2 DVDD D2 VSYNC E2 DOVDD F2 XVCLK1 E3 RESET F3 DOGND A3 SIO_D B3 AGND A4 D2 B4 SIO_C C4 A5 D4 B5 D3 C5 D5 D5 NC E5 D6 F5 D7
*
Ordering Information
Product OV09650-KL1A (Color) Package CSP-28
D0 D1 D1 E1 HREF F1 PCLK
OV9650
NC D4 NC E4 D8 F4 D9
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OV9650
Color CMOS SXGA (1.3 MegaPixel) OmniPixelTM CAMERACHIPTM
Omni
ision
Functional Description
Figure 2 shows the functional block diagram of the OV9650 image sensor. The OV9650 includes: * Image Sensor Array (1300 x 1028 active image array) * Analog Signal Processor * A/D Converters * Digital Signal Processor (DSP) * Output Formatter * Timing Generator * SCCB Interface * Digital Video Port
Figure 2 Functional Block Diagram
G Analog Processing R
MUX
A/D
DSP MUX B
A/D
Formatter
Video Port
D[9:0]
Column Sense Amp Row Select
Exposure/Gain Detect
White Balance Detect
Image Array (1300 x 1028) Registers
Clock
Video Timing Generator Exposure/Gain Control White Balance Control SCCB Interface
XVCLK1
HREF
PCLK
VSYNC RESET
PWDN SIO_C SIO_D
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ision
Functional Description
Image Sensor Array
The OV9650 sensor has an active image array of 1300 columns by 1028 rows (1,336,400 pixels). Figure 3 shows a cross-section of the image sensor array.
In addition to the A/D conversion, this block also has the following functions: * Digital Black-Level Calibration (BLC) * Optional U/V channel delay * Additional A/D range controls In general, the combination of the A/D Range Multiplier and A/D Range Control sets the A/D range and maximum value to allow the user to adjust the final image brightness as a function of the individual application.
Figure 3 Image Sensor Array
Microlens Glass
Digital Signal Processor (DSP)
Blue Green Red
Timing Generator
In general, the timing generator controls the following functions: * Array control and frame generation (7 different format outputs) * Internal timing signal generation and distribution * Frame rate timing * Automatic Exposure Control (AEC) * External timing outputs (VSYNC, HREF/HSYNC, and PCLK)
This block controls the interpolation from Raw data to RGB and some image quality control. * Edge enhancement (a two-dimensional high pass filter) * Color space converter (can change Raw data to RGB or YUV/YCbCr) * RGB matrix to eliminate color cross talk * Hue and saturation control * Programmable gamma control * Transfer 10-bit data to 8-bit * White pixel canceling * De-noise
Output Formatter
This block controls all output and data formatting required prior to sending the image out.
Analog Signal Processor
This block performs all analog image functions including: * Automatic Gain Control (AGC) * Automatic White Balance (AWB)
Digital Video Port
Register bits COM2[1:0] increase IOL/IOH drive current and can be adjusted as a function of the customer's loading.
A/D Converters
After the Analog Processing block, the bayer pattern Raw signal is fed to two 10-bit analog-to-digital (A/D) converters via two multiplexers, one for the G channel and one shared by the BR channels. These A/D converters operate at speeds up to 12 MHz and are fully synchronous to the pixel rate (actual conversion rate is related to the frame rate).
SCCB Interface
The Serial Camera Control Bus (SCCB) interface controls the CAMERACHIP operation. Refer to OmniVision Technologies Serial Camera Control Bus (SCCB) Specification for detailed usage of the serial control port.
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OV9650
Color CMOS SXGA (1.3 MegaPixel) OmniPixelTM CAMERACHIPTM
Omni
ision
Pin Description
Table 1
Pin Location A1 A2 A3 A4 A5 B1 B2 B3 B4 B5 C1 C2 C4 C5 D1 D2 D4 D5 E1 E2 E3 E4 E5 F1 F2 F3 F4 F5 NOTE: D[9:2] for 8-bit YUV or RGB565/RGB555 (D[9] MSB, D[2] LSB) D[9:0] for 10-bit Raw RGB data (D[9] MSB, D[0] LSB) 4 Proprietary to OmniVision Technologies Version 1.91, January 28, 2005
Pin Description
Name PWDN AVDD SIO_D D2 D4 VREF NVDD AGND SIO_C D3 D0 DVDD NC D5 D1 VSYNC NC NC HREF DOVDD RESET D8 D6 PCLK XVCLK1 DOGND D9 D7 Pin Type Function (default = 0) Power I/O Output Output VREF VREF Power Input Output Output Power -- Output Output Output -- -- Output Power Function/Description Power Down Mode Selection - active high, internal pull-down resistor. 0: Normal mode 1: Power down mode Analog power supply (VDD-A = 2.45 to 2.8 VDC) SCCB serial interface data I/O Output bit[2] - LSB for 8-bit YUV or RGB565/RGB555 Output bit[4] Internal voltage reference - connect to ground through 1F capacitor Voltage reference Analog ground SCCB serial interface clock input Output bit[3] Output bit[0] - LSB for 10-bit Raw RGB data only Power supply (VDD-C = 1.8 VDC + 10%) for digital core logic No connection Output bit[5] Output bit[1] - for 10-bit RGB only Vertical sync output No connection No connection HREF output Digital power supply for I/O (VDD-IO = 2.5 to (VDD-A+03.V))
Function Clears all registers and resets them to their default values. Active high, internal (default = 0) pull-down resistor. Output Output Output Input Power Output Output Output bit[8] Output bit[6] Pixel clock output System clock input Digital ground Output bit[9] - MSB for 10-bit Raw RGB data and 8-bit YUV or RGB565/RGB555 Output bit[7]
Omni
ision
Electrical Characteristics
Electrical Characteristics
Table 2 Absolute Maximum Ratings
-40C to +95C VDD-A Supply Voltages (with respect to Ground) VDD-C VDD-IO All Input/Output Voltages (with respect to Ground) Lead-free Temperature, Surface-mount process ESD Rating, Human Body model NOTE: 4.5 V 3V 4.5 V -0.3V to VDD-IO+1V 245C 2000V
Ambient Storage Temperature
Exceeding the Absolute Maximum ratings shown above invalidates all AC and DC electrical specifications and may result in permanent device damage.
Table 3
Symbol VDD-A VDD-C VDD-IO IDDA IDDS-SCCB IDDS-PWDN VIH VIL VOH VOL IOH IOL IL
a. b. c.
DC Characteristics (-20C < TA < 70C)
Parameter DC supply voltage - Analog DC supply voltage - Core DC supply voltage - I/O power Active (Operating) Current Standby Current Standby Current Input voltage HIGH Input voltage LOW Output voltage HIGH Output voltage LOW Output current HIGH Output current LOW Input/Output Leakage GND to VDD-IO See Note c 8 15 1 CMOS 0.9 x VDD-IO 0.1 x VDD-IO Condition - - - See Note a See Note b CMOS 0.7 x VDD-IO 0.3 x VDD-IO Min 2.45 1.62 2.5 Typ 2.5 1.8 - 20 1 10 20 Max 2.8 1.98 VDD-A+0.3V Unit V V V mA mA A V V V V mA mA A
VDD-A = 2.5V, VDD-C = 1.8V, VDD-IO = 2.5V IDDA = {IDD-IO+ IDD-C + IDD-A}, fCLK = 24MHz at 7.5 fps YUV output, no I/O loading VDD-A = 2.5V, VDD-C = 1.8V, VDD-IO = 2.5V IDDS:SCCB refers to a SCCB-initiated Standby, while IDDS:PWDN refers to a PWDN pin-initiated Standby Standard Output Loading = 25pF, 1.2K
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OV9650
Table 4
Symbol
Color CMOS SXGA (1.3 MegaPixel) OmniPixelTM CAMERACHIPTM Functional and AC Characteristics (-20C < TA < 70C)
Parameter A/D A/D AGC Differential Non-Linearity Integral Non-Linearity Range Red/Blue Adjustment Range 12 Min Typ + 1/2 +1 18 Max
Omni
ision
Unit LSB LSB dB dB
Functional Characteristics
Inputs (PWDN, CLK, RESET) fCLK tCLK tCLK:DC tS:RESET tS:REG Input Clock Frequency Input Clock Period Clock Duty Cycle Setting time after software/hardware reset Settling time for register change (10 frames required) 10 21 45 24 42 50 48 100 55 1 300 MHz ns % ms ms
SCCB Timing (see Figure 4) fSIO_C tLOW tHIGH tAA tBUF tHD:STA tSU:STA tHD:DAT tSU:DAT tSU:STO tR, tF tDH Clock Frequency Clock Low Period Clock High Period SIO_C low to Data Out valid Bus free time before new START START condition Hold time START condition Setup time Data-in Hold time Data-in Setup time STOP condition Setup time SCCB Rise/Fall times Data-out Hold time 50 1.3 600 100 1.3 600 600 0 100 600 300 900 400 KHz s ns ns s ns ns s ns ns ns ns
Outputs (VSYNC, HREF, PCLK, and D[9:0] (see Figure 5, Figure 6, Figure 7, Figure 8, Figure 10, and Figure 11) tPDV tSU tHD tPHH tPHL PCLK[] to Data-out Valid D[9:0] Setup time D[9:0] Hold time PCLK[] to HREF[] PCLK[] to HREF[] * VDD: AC Conditions: VDD-C = 1.8V, VDD-A = 2.5V, VDD-IO = 2.5V 5ns, Maximum SCCB: 300ns, Maximum * Input Capacitance: 10pf * Output Loading: 25pF, 1.2K to 2.5V 24MHz * fCLK: Version 1.91, January 28, 2005 15 8 0 0 5 5 5 ns ns ns ns ns
* Rise/Fall Times: I/O:
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Omni
ision
Timing Specifications
Timing Specifications
Figure 4 SCCB Timing Diagram
tF tLOW SIO_C tSU:STA SIO_D IN t BUF tAA SIO_D OUT t DH t HD:STA t HD:DAT t SU:DAT tSU:STO t HIGH tR
Figure 5 Horizontal Timing
tPCLK PCLK
t PHL HREF tSU t HD D[9:0] Last Byte Zero First Byte tPDV Last Byte (Row Data)
tPHL
Figure 6 SXGA Frame Timing
1050 x tLINE VSYNC tLINE = 1520 tP 4 x tLINE HREF 1280 tP 16 tP HSYNC 80 tP 117 tP 43 tP 18453 tP 240 tP 15227 tP
D[9:0]
Invalid Data P0 - P1279
Invalid Data
Row 0 NOTE: For Raw data, tP = internal pixel clock For YUV/RGB, tP = 2 x internal pixel clock
Row 1
Row 2
Row 1023
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Color CMOS SXGA (1.3 MegaPixel) OmniPixelTM CAMERACHIPTM
Omni
ision
Figure 7 VGA Frame Timing
500 x tLINE VSYNC tLINE = 800 tP 4 x tLINE HREF 640 tP 8 tP HSYNC 40 tP 98.5 tP 21.5 tP 6546.5 tP 160 tP 6413.5 tP
D[9:0]
Invalid Data P0 - P639
Invalid Data
Row 0 NOTE: For Raw data, tP = internal pixel clock For YUV/RGB, tP = 2 x internal pixel clock
Row 1
Row 2
Row 479
Figure 8 QVGA Frame Timing
250 x tLINE VSYNC tLINE = 400 tP 2 x tLINE HREF 320 tP 4 tP HSYNC 20 tP 49.5 tP 10.5 tP 2873.5 tP 80 tP 406.5 tP
D[9:0]
Invalid Data P0 - P319
Invalid Data
NOTE: Row 0 For Raw data, tP = internal pixel clock For YUV/RGB, tP = 2 x internal pixel clock
Row 1
Row 2
Row 239
Figure 9 QQVGA Frame Timing
250 x tLINE VSYNC 4 x tLINE HREF (YUV/RGB) 1437 tP 240 tP 403 tP
160 tP tLINE = 200 tP 1837 tP 40 tP 440 tP 203 tP
HREF (Raw Data) 2 tP HSYNC (YUV/RGB) 2 tP HSYNC (Raw Data) P0 - P159 D[9:2] (YUV/RGB) Invalid Data Row 0 25 tP
160 tP 5 tP 25 tP 5 tP 10 tP 5 tP 10 tP
160 tP
10 tP
10 tP
Invalid Data Row 1 Row 2 Row 3 Row 119
D[9:0] (Raw Data) NOTE: For YUV/RGB, tP = 2 x tPCLK For Raw data, tP = tPCLK
Invalid Data Row 0 Row 1 Row 2 Row 3 Row 118 Row 119
Invalid Data
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ision
Timing Specifications
Figure 10 CIF Frame Timing
384 x tLINE VSYNC tLINE = 520 tP 4 x tLINE HREF 352 tP 8 tP HSYNC 40 tP 98.5 tP 29.5 tP 4306.5 tP 168 tP 43701.5 tP
D[9:0]
Invalid Data P0 - P351
Invalid Data
NOTE: Row 0 For Raw data, tP = internal pixel clock For YUV/RGB, tP = 2 x internal pixel clock
Row 1
Row 2
Row 287
Figure 11 QCIF Frame Timing
192 x tLINE VSYNC tLINE = 260 tP 4 x tLINE HREF 176 tP 4 tP HSYNC 20 tP 49.5 tP 14.5 tP 2153.5 tP 84 tP 9370.5 tP
D[9:0]
Invalid Data
Invalid Data
P0 - P175 NOTE: Row 0 For Raw data, tP = internal pixel clock For YUV/RGB, tP = 2 x Internal pixel clock
Row 1
Row 2
Row 143
Figure 12 QQCIF Frame Timing
192 x tLINE VSYNC 4 x tLINE HREF (YUV/RGB) 1077 tP 172 tP 4815 tP
88 tP tLINE = 130 tP 1337 tP 42 tP 302 tP 4685 tP
HREF (Raw Data) 2 tP HSYNC (YUV/RGB) HSYNC (Raw Data) 2 tP 25 tP 7 tP
88 tP 7 tP 10 tP 7 tP 10 tP
88 tP
10 tP
25 tP
P0 - P87 D[9:2] (YUV/RGB) Invalid Data Row 0
10 tP
Invalid Data Row 1 Row 2 Row 3 Row 71
D[9:0] (Raw Data) NOTE: For YUV/RGB, tP = 2 x tPCLK For Raw data, tP = tPCLK
Invalid Data Row 0 Row 1 Row 2 Row 3 Row 70 Row 71
Invalid Data
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OV9650
Color CMOS SXGA (1.3 MegaPixel) OmniPixelTM CAMERACHIPTM
Omni
ision
Figure 13 RGB 565 Output Timing Diagram
tPCLK PCLK
t PHL HREF tSU t HD D[9:2] Last Byte tPDV First Byte Last Byte (Row Data)
tPHL
First Byte D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] R0 G5 G3 R4
Second Byte G2 G0 B4 D[9] D[8] D[7] D[6] D[5] D[4] D[3] B0 D[2]
Figure 14 RGB 555 Output Timing Diagram
tPCLK PCLK
t PHL HREF tSU t HD D[9:2] Last Byte tPDV First Byte Last Byte (Row Data)
tPHL
First Byte D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] R0 G4 G3 X R4
Second Byte G2 G0 B4 D[9] D[8] D[7] D[6] D[5] D[4] D[3] B0 D[2]
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ision
Timing Specifications
OV9650 Light Response
Figure 15 OV9650 Light Response
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OV9650 Register Set
Color CMOS SXGA (1.3 MegaPixel) OmniPixelTM CAMERACHIPTM
Omni
ision
Table 5 provides a list and description of the Device Control registers contained in the OV9650. For all register Enable/Disable bits, ENABLE = 1 and DISABLE = 0. The device slave addresses are 60 for write and 61 for read.
Table 5
Address (Hex) 00
Device Control Register List
Register Name GAIN Default (Hex) 00 R/W RW Description AGC[7:0] - Gain control gain setting * Range: [00] to [FF] AWB - Blue channel gain setting * Range: [00] to [FF] AWB - Red channel gain setting * Range: [00] to [FF] Vertical Frame Control
01
BLUE
80
RW
02
RED
80
RW
03
VREF
12
RW
Bit[7:6]: Bit[5:3]: Bit[2:0]:
AGC[9:8] (see register GAIN for AGC[7:0]) VREF end low 3 bits (high 8 bits at VSTOP[7:0] VREF start low 3 bits (high 8 bits at VSTRT[7:0]
Common Control 1 Bit[7]: Bit[6]: Bit[5]: Reserved CCIR656 format QQVGA or QQCIF format. Effective only when QVGA (register bit COM7[4]) or QCIF (register bit COM7[3]) output is selected and related HREF skip option based on format is selected (register COM1[3:2]) Reserved HREF skip option 00: No skip 01: YUV/RGB skip every other row for YUV/RGB, skip 2 rows for every 4 rows for Raw data 1x: Skip 3 rows for every 4 rows for YUV/RGB, skip 6 rows for every 8 rows for Raw data AEC low 2 LSB (see registers AECHM for AEC[15:10] and AECH for AEC[9:2])
04
COM1
00
RW
Bit[4]: Bit[3:2]:
Bit[1:0]:
05 06 07 08
BAVE GEAVE RSVD RAVE
00 00 00 00
RW RW - RW
U/B Average Level Automatically updated based on chip output format Y/Ge Average Level Automatically updated based on chip output format Reserved V/R Average Level Automatically updated based on chip output format
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ision
Register Set
Table 5
Address (Hex)
Device Control Register List (Continued)
Register Name Default (Hex) R/W Common Control 2 Bit[7:5]: Bit[4]: Bit[3:2]: Bit[1:0]: Reserved Soft sleep mode Reserved Output drive capability 00: 1x 01: 2x 10: 2x 11: 4x Description
09
COM2
01
RW
0A 0B
PID VER
96 52
R R
Product ID Number MSB (Read only) Product ID Number LSB (Read only) Common Control 3 Bit[7]: Bit[6]: Bit[5:4]: Bit[3]: Reserved Output data MSB and LSB swap Reserved Pin selection 1: Change RESET pin to EXPST_B (frame exposure mode timing) and change PWDN pin to FREX (frame exposure enable) VarioPixel for VGA, CIF, QVGA, QCIF, QQVGA, and QQCIF Reserved Single frame output (used for Frame Exposure mode only)
0C
COM3
00
RW Bit[2]: Bit[1]: Bit[0]:
Common Control 4 Bit[7]: Bit[6:3]: Bit[2]: 0D COM4 00 RW Bit[1]: VarioPixel for QVGA, QCIF, QQVGA, and QQCIF Reserved Tri-state option for output clock at power-down period 0: Tri-state at this period 1: No tri-state at this period Tri-state option for output data at power-down period 0: Tri-state at this period 1: No tri-state at this period Reserved
Bit[0]:
Common Control 5 Bit[7]: 0E COM5 01 RW Bit[6:5]: Bit[4]: System clock selection. If the system clock is 48 MHz, this bit should be set to high to get 15 fps for YUV or RGB Reserved Slam mode enable 0: Master mode 1: Slam mode (used for slave mode) Reserved
Bit[3:0]:
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Table 5
Address (Hex)
Color CMOS SXGA (1.3 MegaPixel) OmniPixelTM CAMERACHIPTM Device Control Register List (Continued)
Register Name Default (Hex) R/W Common Control 6 Bit[7]: Output of optical black line option 0: Disable HREF at optical black 1: Enable HREF at optical black Reserved Enable bias for ADBLC ADBLC offset 0: Use 4-channel ADBLC 1: Use 2-channel ADBLC Reset all timing when format changes Enable ADBLC option Description
Omni
ision
0F
COM6
43
RW
Bit[6:4]: Bit[3]: Bit[2]:
Bit[1]: Bit[0]: 10 AECH 40 RW
Exposure Value Bit[7:0]: AEC[9:2] (see registers AECHM for AEC[15:10] and COM1 for AEC[1:0])
Data Format and Internal Clock Bit[7]: Digital PLL option 0: Disable double clock option, meaning the maximum PCLK can be as high as half input clock 1: Enable double clock option, meaning the maximum PCLK can be as high as input clock Use input clock directly (no clock pre-scale available) Internal clock pre-scalar F(internal clock) = F(input clock)/(Bit[5:0]+1) * Range: [0 0000] to [1 1111]
11
CLKRC
00
RW Bit[6]: Bit[5:0]:
Common Control 7 Bit[7]: SCCB Register Reset 0: No change 1: Resets all registers to default values Output format - VGA selection Output format - CIF selection Output format - QVGA selection Output format - QCIF selection Output format - RGB selection Reserved Output format - Raw RGB (COM7[2] must be set high)
12
COM7
00
RW
Bit[6]: Bit[5]: Bit[4]: Bit[3]: Bit[2]: Bit[1]: Bit[0]:
Common Control 8 Bit[7]: Bit[6]: 13 COM8 8F RW Enable fast AGC/AEC algorithm AEC - Step size limit 0: Fast condition change maximum step is VSYNC 1: Unlimited step size Banding filter ON/OFF Reserved AGC Enable AWB Enable AEC Enable
Bit[5]: Bit[4:3]: Bit[2]: Bit[1]: Bit[0]:
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ision
Register Set
Table 5
Address (Hex)
Device Control Register List (Continued)
Register Name Default (Hex) R/W Common Control 9 Bit[7]: Bit[6:4]: Reserved Automatic Gain Ceiling - maximum AGC value 000: 2x 001: 4x 010: 8x 011: 16x 100: 32x 101: 64x 110: 128x Exposure timing can be less than limit of banding filter when light is too strong Data format - VSYNC drop option 0: VSYNC always exists 1: VSYNC will drop when frame data drops Enable drop frame when AEC step is larger than the Exposure Gap Freeze AGC/AEC Description
14
COM9
4A
RW Bit[3]: Bit[2]:
Bit[1]: Bit[0]:
Common Control 10 Bit[7]: Set pin definition 1: Set RESET to SLHS (slave mode horizontal sync) and set PWDN to SLVS (slave mode vertical sync) HREF changes to HSYNC PCLK output option 0: PCLK always output 1: No PCLK output when HREF is low PCLK reverse HREF reverse Reset signal end point option VSYNC negative HSYNC negative
Bit[6]: Bit[5]: 15 COM10 00 RW Bit[4]: Bit[3]: Bit[2]: Bit[1]: Bit[0]: 16 17 18 19 1A RSVD HSTART HSTOP VSTRT VSTOP 00 1A BA 01 81 - RW RW RW RW Reserved
Output Format - Horizontal Frame (HREF column) start high 8-bit (low 3 bits are at HREF[2:0]) Output Format - Horizontal Frame (HREF column) end high 8-bit (low 3 bits are at HREF[5:3]) Output Format - Vertical Frame (row) start high 8-bit (low 3 bits are at VREF[2:0]) Output Format - Vertical Frame (row) end high 8-bit (low 3 bits are at VREF[5:3]) Data Format - Pixel Delay Select (delays timing of the D[9:0] data relative to HREF in pixel units) * Range: [00] (no delay) to [FF] (256 pixel delay which accounts for whole array) Manufacturer ID Byte - High (Read only = 0x7F)
1B
PSHFT
00
RW
1C
MIDH
7F
R
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OV9650
Table 5
Address (Hex) 1D
Color CMOS SXGA (1.3 MegaPixel) OmniPixelTM CAMERACHIPTM Device Control Register List (Continued)
Register Name MIDL Default (Hex) A2 R/W R Manufacturer ID Byte - Low Mirror/VFlip Enable Bit[7:6]: Bit[5]: Reserved Mirror 0: Normal image 1: Mirror image VFlip enable 0: VFlip disable 1: VFlip enable Reserved Description (Read only = 0xA2)
Omni
ision
1E
MVFP
00
RW Bit[4]:
Bit[3:0]: 1F LAEC 00 RW Reserved
B Channel ADBLC Result Bit[7]: 20 BOS 80 RW Bit[6:0]: Offset adjustment sign 0: Add offset 1: Subtract offset Offset value of 10-bit range (high 7 bits)
Gb channel ADBLC result Bit[7]: 21 GBOS 80 RW Bit[6:0]: Offset adjustment sign 0: Add offset 1: Subtract offset Offset value of 10-bit range
Gr channel ADBLC result Bit[7]: 22 GROS 80 RW Bit[6:0]: Offset adjustment sign 0: Add offset 1: Subtract offset Offset value of 10-bit range
R channel ADBLC result Bit[7]: 23 ROS 80 RW Bit[6:0]: 24 25 26 AEW AEB VPT 78 68 D4 RW RW RW Offset adjustment sign 0: Add offset 1: Subtract offset Offset value of 10-bit range
AGC/AEC - Stable Operating Region (Upper Limit) AGC/AEC - Stable Operating Region (Lower Limit) AGC/AEC Fast Mode Operating Region Bit[7:4]: Bit[3:0]: High nibble of upper limit High nibble of lower limit
B Channel Signal Output Bias (effective only when COM6[0] = 1) Bit[7]: 27 BBIAS 80 RW Bit[6:0]: Bias adjustment sign 0: Add bias 1: Subtract bias Bias value of 10-bit range
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ision
Register Set
Table 5
Address (Hex)
Device Control Register List (Continued)
Register Name Default (Hex) R/W Description Gb Channel Signal Output Bias (effective only when COM6[0] = 1) Bit[7]:
28
GbBIAS
80
RW Bit[6:0]:
Bias adjustment sign 0: Add bias 1: Subtract bias Bias value of 10-bit range
Analog BLC and Regulator Control 29 Gr_COM 00 RW Bit[7:6]: Bit[5]: Bit[4]: Bit[3:0]: Reserved Bypass Analog BLC Bypass regulator Reserved
Dummy Pixel Insert MSB 2A EXHCH 00 RW Bit[7]: Bit[6:4]: Bit[3:2]: Bit[1:0]: Reserved 3 MSB for dummy pixel insert in horizontal direction HSYNC falling edge delay 2 MSB HSYNC rising edge delay 2 MSB
2B
EXHCL
00
RW
Dummy Pixel Insert LSB 8 LSB for dummy pixel insert in horizontal direction R Channel Signal Output Bias (effective only when COM6[0] = 1) Bit[7]:
2C
RBIAS
80
RW Bit[6:0]:
Bias adjustment sign 0: Add bias 1: Subtract bias Bias value of 10-bit range
2D 2E 2F 30 31
ADVFL ADVFH YAVE HSYST HSYEN
00 00 00 08 30
RW RW RW RW RW
LSB of insert dummy lines in vertical direction (1 bit equals 1 line) MSB of insert dummy lines in vertical direction Y/G Channel Average Value HSYNC Rising Edge Delay (low 8 bits) HSYNC Falling Edge Delay (low 8 bits) HREF Control
32
HREF
A4
RW
Bit[7:6]: HREF edge offset to data output Bit[5:3]: HREF end 3 LSB (high 8 MSB at register HSTOP) Bit[2:0]: HREF start 3 LSB (high 8 MSB at register HSTART) Bit[7:0]: Bit[7:0]: Reserved Bit[7:0]: Bit[7:0]: Bit[7:4]: Bit[3]: Bit[2:0]: Reserved Reserved Reserved Line buffer power down - must be set to "1" before chip power down Reserved 17 Reserved Reserved
33 34 35-36 37 38
CHLF ARBLM RSVD ADC ACOM
00 03 XX 04 12
RW RW - RW RW
39
OFON
00
RW
Version 1.91, January 28, 2005
Proprietary to OmniVision Technologies
OV9650
Table 5
Address (Hex)
Color CMOS SXGA (1.3 MegaPixel) OmniPixelTM CAMERACHIPTM Device Control Register List (Continued)
Register Name Default (Hex) R/W Line Buffer Test Option Bit[7:6]: Bit[5]: Bit[4]: Description
Omni
ision
3A
TSLB
0C
RW
Bit[3:2]:
Bit[1]: Bit[0]:
Reserved Bit-wise reverse UV output value 0: Use normal UV output 1: Use fixed UV value set in registers MANU and MANV as UV output instead of chip output Output sequence is Y U Y V instead of U Y V Y 00: Y U Y V 01: Y V Y U 10: V Y U Y 11: U Y V Y Reserved Digital BLC enable 0: Disable 1: Enable
Common Control 11 Bit[7]: Night mode 0: Night mode disable 1: Night mode enable - If the AGC gain goes over 2, then AGC gain drops to 0 and frame rate changes by half. COM11[6:5] limits the minimum frame rate. Also, ADVFH and ADVFL will be automatically updated. Night mode insert frame option 00: Normal frame rate 01: 1/2 frame rate 10: 1/4 frame rate 11: 1/8 frame rate Average calculation window option 00: Use full frame 01: Use half frame 10: Use quarter frame 11: Not allowed Reserved Manual banding filter mode
Bit[6:5]: 3B COM11 00 RW Bit[4:3]:
Bit[2:1]: Bit[0]:
Common Control 12 Bit[7]: 3C COM12 40 RW Bit[6:3]: Bit[2]: Bit[1:0]: HREF option 0: No HREF when VREF is low 1: Always has HREF Reserved Enable UV average Reserved
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Version 1.91, January 28, 2005
Omni
ision
Register Set
Table 5
Address (Hex)
Device Control Register List (Continued)
Register Name Default (Hex) R/W Common Control 13 Bit[7:6]: Gamma selection for signal 00: No gamma function 01: Gamma used for Y channel only 10: Gamma used for Raw data before interpolation 11: Not allowed Reserved Enable color matrix for RGB or YUV Enable Y channel delay option 0: Delay UV channel 1: Delay Y channel Output Y/UV delay Description
3D
COM13
99
RW
Bit[5]: Bit[4]: Bit[3]:
Bit[2:0]:
Common Control 14 Bit[7:2]: Bit[1]: 3E COM14 0E RW Bit[0]: Reserved Enable edge enhancement for YUV output (effective only for YUV/RGB, no use for Raw data) Edge enhancement option 0: Edge enhancement factor = EDGE[3:0] 1: Edge enhancement factor = 2 x EDGE[3:0]
Edge Enhancement Adjustment 3F EDGE 88 RW Bit[7:4]: Bit[3:0]: Edge enhancement threshold[3:0] (see register COM22[7:6} for Edge threshold[5:4]) Edge enhancement factor
Common Control 15 Bit[7:6]: Data format - output full range enable 0x: Output range: [10] to [F0] 10: Output range: [01] to [FE] 11: Output range: [00] to [FF] RGB 555/565 option (must set COM7[2] high) x0: Normal RGB output 01: RGB 565 11: RGB 555 Swap R/B in RGB565/RGB555 format Reserved
40
COM15
C0
RW
Bit[5:4]:
Bit[3]: Bit[2:0]:
Common Control 16 41 COM16 10 RW Bit[7:2]: Bit[1]: Bit[0]: Reserved Color matrix coefficient double option Reserved
Common Control 17 Bit[7:5]: Bit[4]: Bit[3]: Bit[2]: Bit[1]: Bit[0]: Reserved Edge enhancement option Reserved Select single frame out Tri-state output after single frame out Reserved
42
COM17
08
RW
Version 1.91, January 28, 2005
Proprietary to OmniVision Technologies
19
OV9650
Table 5
Address (Hex) 43-4E 4F 50 51 52 53 54 55 56 57 58 59-61 62 63 64 65 66 67 68 69 6A 6B 6C-7B 7C-8A 8B
Color CMOS SXGA (1.3 MegaPixel) OmniPixelTM CAMERACHIPTM Device Control Register List (Continued)
Register Name RSVD MTX1 MTX2 MTX3 MTX4 MTX5 MTX6 MTX7 MTX8 MTX9 MTXS RSVD LCC1 LCC2 LCC3 LCC4 LCC5 MANU MANV HV MBD DBLV GSP GST COM21 Default (Hex) XX 58 48 10 28 48 70 40 40 40 0F XX 00 00 10 80 00 80 80 00 00 0A XX XX 04 R/W - RW RW RW RW RW RW RW RW RW RW - RW RW RW RW RW RW RW RW RW RW RW RW RW Reserved Matrix Coefficient 1 Matrix Coefficient 2 Matrix Coefficient 3 Matrix Coefficient 4 Matrix Coefficient 5 Matrix Coefficient 6 Matrix Coefficient 7 Matrix Coefficient 8 Matrix Coefficient 9 Matrix Coefficient Sign for coefficient 9 to 2 0: Plus 1: Minus Reserved Lens Correction Option 1 Lens Correction Option 2 Lens Correction Option 3 Lens Correction Option 4 Lens Correction Control Description
Omni
ision
Manual U Value (effective only when register TSLB[4] is high) Manual V Value (effective only when register TSLB[4] is high) Manual Banding Filter MSB Bit[7:1]: Bit[0]: Reserved Matrix coefficient 1 sign
Manual Banding Filter Value (effective only when COM11[0] is high). Bit[7:0]: Gamma curve Gamma curve Common Control 21 Bit[7:0]: Reserved Reserved
20
Proprietary to OmniVision Technologies
Version 1.91, January 28, 2005
Omni
ision
Register Set
Table 5
Address (Hex)
Device Control Register List (Continued)
Register Name Default (Hex) R/W Common Control 22 Bit[7:6]: Edge enhancement threshold[5:4] (see register EDGE[7:4} for Edge threshold[3:0]) De-noise enable Reserved White-pixel erase enable White-pixel erase option Description
8C
COM22
00
RW
Bit[5]: Bit[4:2]: Bit[1]: Bit[0]:
Common Control 23 Bit[7:5]: Bit[4]: Bit[3:2]: Bit[1]: Reserved Color bar test mode Reserved Color gain option 0: Analog 1: Digital Reserved
8D
COM23
00
RW
Bit[0]: 8E COM24 00 RW
Common Control 24 Bit[7:0]: Reserved
Digital BLC Offset Sign Bit[7:4]: Bit[3]: Bit[2]: Bit[1]: Bit[0]: Reserved Digital BLC B offset sign Digital BLC R offset sign Digital BLC Gb offset sign Digital BLC Gr offset sign
8F
DBLC1
0F
RW
90
DBLC_B
00
RW
Digital BLC B Channel Offset Value Bit[7:0]: Digital BLC B channel offset value
91
DBLC_R
00
RW
Digital BLC R Channel Offset Value Bit[7:0]: Digital BLC R channel offset value
92
DM_LNL
00
RW
Dummy Line low 8 bits Bit[7:0]: Control insert Dummy line[7:0]
93 94-9C 9D 9E 9F
DM_LNH RSVD LCCFB LCCFR DBLC_Gb
00 XX 00 00 00
RW - RW RW RW
Dummy Line high 8 bits Bit[7:0]: Reserved Lens Correction B Channel Control Lens Correction R Channel Control Digital BLC Gb Channel Offset Value Bit[7:0]: Digital BLC Gb channel offset value Control insert Dummy line[15:8]
A0
DBLC_Gr
00
RW
Digital BLC Gr Channel Offset Value Bit[7:0]: Digital BLC Gr channel offset value
Version 1.91, January 28, 2005
Proprietary to OmniVision Technologies
21
OV9650
Table 5
Address (Hex)
Color CMOS SXGA (1.3 MegaPixel) OmniPixelTM CAMERACHIPTM Device Control Register List (Continued)
Register Name Default (Hex) R/W Description Exposure Value - AEC MSB 5 bits
Omni
ision
A1
AECHM
40
RW
Bit[7:6]: Bit[5:0]: Reserved
Reserved AEC[15:10] (see registers AECH for AEC[9:2] and COM1 for AEC[1:0])
A2-A3 A4
RSVD COM25
XX 00
- RW
Common Control 25 Bit[7:0]: Reserved
A5 A6 A7 A8-AA
COM26 G_GAIN VGA_ST ACOM
00 80 14 XX
RW RW RW -
Common Control 26 Bit[7:0]: Reserved Reserved Reserved Reserved
NOTE: All other registers are factory-reserved. Please contact OmniVision Technologies for reference register settings.
22
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Version 1.91, January 28, 2005
Omni
ision
Package Specifications
Package Specifications
The OV9650 uses a 28-pin Chip Scale Package (CSP). Refer to Figure 16 for package information, Table 6 for package dimensions and Figure 17 for the array center on the chip.
Note: For OVT devices that contain lead, all part marking letters are upper case. For OVT devices that are lead-free, all part marking letters are lower case Figure 16 OV9650 Package Specifications
A 1 2 3 4 5 S2 A J2 B B A S1 5 J1 4 3 2 1 A1 Ball Indicator
WXYZ AB CD
C B D
C
D
E
E
F
F
Top View (Bumps Down) Center of BGA (die) = Center of the package Glass C2 Die C3
Bottom View (Bumps Up)
C C1 Side View
Part Marking Code: W - OVT Product Version X - Year the part is assembled Y - Month the part is assembled Z - Wafer number ABCD - Last four digits of lot number
Table 6
CSP Package Dimensions Parameter Symbol
A B C C1 C2 C3 D N N1 N2 J1 J2 S1 S2 918 828
Min
5070 5690 760 150 605 395 320
Nominal
5095 5715 820 180 640 415 350 28 (3 NC) 5 6 800 800 948 858
Max
5120 5740 880 210 675 435 380
Unit
m m m m m m m
Package Body Dimension X Package Body Dimension Y Package Height Ball Height Package Body Thickness Thickness of Glass Surface to Wafer Ball Diameter Total Pin Count Pin Count X-axis Pin Count Y-axis Pins Pitch X-axis Pins Pitch Y-axis Edge-to-Pin Center Distance Analog X Edge-to-Pin Center Distance Analog Y Version 1.91, January 28, 2005
m m 978 888 m m 23
Proprietary to OmniVision Technologies
OV9650
Color CMOS SXGA (1.3 MegaPixel) OmniPixelTM CAMERACHIPTM
Omni
ision
Sensor Array Center
Figure 17 OV9650 Sensor Array Center
A1
A2
A3
A4
A5
4134 m
3275 m
Package Center (0,0)
Sensor Array
OV9650 Array Center (-59.4 m, 348.4 m)
NOTES: 1. This drawing is not to scale and is for reference only. 2. As most optical assemblies invert and mirror the image, the chip is typically mounted with pins A1 to A5 oriented down on the PCB.
The recommended lens chief ray angle for the OV9650 is 20 degrees.
24
Proprietary to OmniVision Technologies
Version 1.91, January 28, 2005
Omni
ision
Package Specifications
IR Reflow Ramp Rate Requirements OV9650 Lead-Free Packaged Devices
Note: For OVT devices that are lead-free, all part marking letters are lower case Figure 18 IR Reflow Ramp Rate Requirements
300.0 280.0 260.0 240.0 220.0 200.0 Temperature ( ) C 180.0 160.0 140.0 120.0 100.0 80.0 60.0 40.0 20.0 0.0 0.0 -22 -2 18 38 0.6 58 78 1.1 98 118 1.6 138 158 2.2 178 198 Time (sec) -0.3 -0.1 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 2.8 218 238 3.3 258 278 3.9 298 318 338 358 369 Z1 Z2 Z3 Z4 Z5 Z6 Z7 end
Time (min.)
Table 7
Reflow Conditions
Condition Exposure Less than 3C per second Between 330 - 600 seconds At least 210 seconds At least 30 seconds (30 ~ 120 seconds) 245C Less than 6C per second No greater than 390 seconds
Average Ramp-up Rate (30C to 217C) > 100C > 150C > 217C Peak Temperature Cool-down Rate (Peak to 50C) Time from 30C to 255C
Environmental Specifications Table 8 OV9650 Reliability Test Results
Parameter Temperature/Humidity Temperature Cycling (Air-to-Air) Highly Accelerated Stress Test (HAST) High Temperature Storage (HTS) High Temperature Static Bias (HTSB)
a.
Test Condition 85C/85% Relative Humidity, 1000 hrs.a -25C / +125C, 72 cycles/day, 1000 cyclesa 110C / 85% Relative Humidity, 168 hrs.a 150C, 1000 hrs.a 125C, 1000 hrs.a
Pre-Condition (Moisture Level II): 125C, 24h 85C/60% RH/168h IR Reflow 235C, 10 sec, 3 cycles
Version 1.91, January 28, 2005
Proprietary to OmniVision Technologies
25
OV9650
Color CMOS SXGA (1.3 MegaPixel) OmniPixelTM CAMERACHIPTM
Omni
ision
Note:
* All information shown herein is current as of the revision and publication date. Please refer to the OmniVision web site (http://www.ovt.com) to obtain the current versions of all documentation. OmniVision Technologies, Inc. reserves the right to make changes to their products or to discontinue any product or service without further notice (It is advisable to obtain current product documentation prior to placing orders). Reproduction of information in OmniVision product documentation and specifications is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. In such cases, OmniVision is not responsible or liable for any information reproduced. This document is provided with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any warranty otherwise arising out of any proposal, specification or sample. Furthermore, OmniVision Technologies Inc. disclaims all liability, including liability for infringement of any proprietary rights, relating to use of information in this document. No license, expressed or implied, by estoppels or otherwise, to any intellectual property rights is granted herein. `OmniVision', `CameraChip', and 'VarioPixel' are trademarks of OmniVision Technologies, Inc. All other trade, product or service names referenced in this release may be trademarks or registered trademarks of their respective holders. Third-party brands, names, and trademarks are the property of their respective owners.
*
*
*
*
For further information, please feel free to contact OmniVision at info@ovt.com.
OmniVision Technologies, Inc. 1341 Orleans Drive Sunnyvale, CA USA (408) 542-3000
26
Proprietary to OmniVision Technologies
Version 1.91, January 28, 2005

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